1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in which both a high-breakdown-voltage MOS (Metal Oxide Semiconductor) transistor and a low-breakdown-voltage MOS transistor having different drain breakdown voltages are formed on an identical substrate.
2. Description of the Related Art
An integrated circuit for actuating, for example, an imaging element, an LCD (Liquid Crystal Display), or a print head (hereinafter referred to as the xe2x80x98actuation ICxe2x80x99) generally includes an actuation output module with a high-breakdown-voltage MOS transistor, which is driven by a power supply voltage of 10 or greater volts and has a high withstand voltage between a drain and a source (hereinafter may be referred to as the xe2x80x98drain breakdown voltagexe2x80x99), and a logic module with a low-breakdown-voltage MOS transistor, which is driven by a power supply voltage of several or less volts and has a low drain breakdown voltage, for controlling the actuation output module. In the description below, the MOS transistor may be simply called the transistor.
In the actuation IC, it is preferable that the high-breakdown-voltage transistor and the low-breakdown-voltage transistor are formed on an identical substrate. The simplest method of forming such transistors of different withstand voltages on an identical substrate is to separately form the respective transistors according to different processes. The method first forms one of the high-breakdown-voltage transistor and the low-breakdown-voltage transistor on a substrate, and subsequently forms the other transistor on the same substrate.
The method of separately forming the high-breakdown-voltage transistor and the low-breakdown-voltage transistor, however, significantly increases the total number of manufacturing steps, thus worsening the production efficiency and increasing the manufacturing cost.
There is accordingly a demand for efficiently forming both a high-breakdown-voltage transistor and a low-breakdown-voltage transistor on an identical substrate without damaging the characteristics of the respective transistors.
The object of the present invention is thus to solve the drawback of the prior art technique discussed above and to provide a technique of efficiently forming both a high-breakdown-voltage transistor and a low-breakdown-voltage transistor on an identical substrate without damaging the characteristics of the respective transistors.
In order to attain at least part of the above and the other related objects, the present invention is directed to a method of manufacturing a semiconductor device, in which both a high-breakdown-voltage MOS transistor and a low-breakdown-voltage MOS transistor having different drain breakdown voltages are formed on an identical semiconductor substrate. The manufacturing method includes the steps of: (a) forming a gate electrode on a first dielectric film created above the substrate, creating a second dielectric film over surface of the substrate including the gate electrode, and etching the second dielectric film, so as to define a side wall of the second dielectric film on a side face of the gate electrode; and (b) implanting an impurity to specify a drain area and a source area, The step (b) includes the sub-steps of: (b-1) forming a first mask that keeps open at least a drain-source forming region in the high-breakdown-voltage MOS transistor, which is expected to form a drain area and a source area, and covers over at least an offset forming region in the high-breakdown-voltage MOS transistor, which is expected to form an offset area between the gate electrode and either one of the drain area and the source area; (b-2) using the first mask and etching off a dielectric film part at least on the drain-source forming region, out of the dielectric film created on the substrate; and (b-3) continuously using the same first mask and implanting the impurity into the drain-source forming region.
The manufacturing method of the present invention enables both the high-breakdown-voltage MOS transistor and the low-breakdown-voltage MOS transistor to be efficiently formed on an identical substrate. The arrangement of the manufacturing method effectively prevents the impurity ion from being implanted into a lower layer under the dielectric film in the vicinity of the gate electrode in the high-breakdown-voltage MOS transistor to define the drain area and the source area. This prevents a decrease in drain breakdown voltage and does not damage the voltage characteristics of the high-breakdown-voltage MOS transistor.
The manufacturing method of the invention continuously uses the same mask without any temporary detachment in the process of etching off the dielectric film on the drain-source forming region in the high-breakdown-voltage MOS transistor and in the process of implanting the impurity ion into the drain-source forming region. There is accordingly no possibility of positional shift of the mask. This arrangement thus ensures accurate implantation of the impurity into the target region.
In accordance with one preferable application of the manufacturing method, the step (a) creates the second dielectric film in a greater thickness than a predetermined standard thickness. The sub-step (b-1) forms the first mask that keeps open an element forming region in the low-breakdown-voltage MOS transistor, on which an element is to be generated, in addition to the drain-source forming region. The sub-step (b-3) implants the impurity into the element forming region as well as into the drain-source forming region.
In the manufacturing method of the invention, it is preferable that the predetermined standard thickness is approximately 1300 angstrom.
The above application enables implantation of the impurity into the drain-source forming region in the high-breakdown-voltage MOS transistor to be carried out simultaneously with implantation of the impurity into the element forming region in the low-breakdown-voltage MOS transistor. This arrangement desirably reduces the total number of processing steps.
The side wall is composed of the second dielectric film having a greater thickness than the standard thickness. Even if part of the side wall in the low-breakdown-voltage MOS transistor is etched off in the process of etching off the dielectric film on the drain-source forming region in the high-breakdown-voltage MOS transistor, this arrangement ensures a desired resulting film thickness required for the side wall.
The thicker second dielectric film for defining the side wall allows a decrease in resulting thickness of the remaining dielectric film in the high-breakdown-voltage MOS transistor on the substrate after etching. This arrangement reduces the amount of etching off the dielectric film on the drain-source forming region in the high-breakdown-voltage MOS transistor to open the drain-source forming region. Such reduction results in decreasing the amount of etching the side wall in the low-breakdown-voltage MOS transistor.
In accordance with another preferable application of the manufacturing method, the sub-step (b-1) forms the first mask that covers over an element forming region in the low-breakdown-voltage MOS transistor, on which an element is to be generated, in addition to the offset forming region. The step (b) further includes the sub-steps of: (b-4) forming a second mask that keeps open at least the element forming region in the low-breakdown-voltage MOS transistor; and (b-5) using the second mask and implanting the impurity into at least the element forming region.
The first mask, which also covers the element forming region in the low-breakdown-voltage MOS transistor, is used in the process of etching off the dielectric film on the drain-source forming region in the high-breakdown-voltage MOS transistor. The element forming region in the low-breakdown-voltage MOS transistor is accordingly not at all affected by etching. No part of the side wall is etched off in the low-breakdown-voltage MOS transistor.
The above arrangement also enables the thickness of the side wall composed of the second dielectric film to be regulated accurately.
In one preferable embodiment of the present invention, the manufacturing method further includes the step of: (c) forming a metal film on the gate electrode, the drain area, and the source area and carrying out heat treatment, so that at least part of semiconductor layers constructing the gate electrode, the drain area, and the source area is fused to a metal of the metal film and is thereby silicidated. The step (c) has the sub-step of: (c-1) generating a protective film at least over the offset forming region.
This arrangement effectively prevents silicidation of the semiconductor in the lower layer under the dielectric film in the vicinity of the gate electrode in the high-breakdown-voltage MOS transistor. The arrangement accordingly prevents a decrease in drain breakdown voltage due to silicidation of the semiconductor in the lower layer and does not damage the voltage characteristics of the high-breakdown-voltage MOS transistor.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with the accompanying drawings.